Pin Descriptions

The CF1 interfaces to your circuitry using three standard double-row 0.1" headers. Many CF1 based systems will only need to access the signals on the 2x25 pin "C" connector, which brings out pins on both sides of board (OEM versions may specify pins on only one side or the other).The 2x10 "A" and "B" connectors bring out the address and data bus along with control signals for system expansion.

The first ten pins of connector "C" form a standard BDM (Background Debugger Mode) connector block at the top of the CF1, and these are identified by a solid white silk-screen. In addition, every fifth pin of connector "C" is marked with white to help quickly identify the proper pin.

Pin type designations are taken from the MC68CK338 Technical Summary, and where appropriate, suffixed with the value of onboard pullup resistors or special notes.

Static Sensitive CMOS!  All of the CF1 pins connect to static sensitve CMOS circuitry. You must take precautions to guard against damage to these parts from static electricity.

Digital I/O

All of the CF1's Digital I/O lines come out on Connector C, the 50 pin header. However, not all pins on Connector C can be used as I/O lines. Furthermore, there are many different kinds of I/O lines and they each have alternate functions that you may wish to use, which precludes them from use as a general-purpose I/O line. There are six main types of pins:

BDM:
These pins are used by Motorola's background debugging mode. These will be of little use to the end user and are primarily used for testing and quality assurance at the factory.

PWR:
These pins are related to the power supply and cannot be used as general purpose I/O. Be careful with the VBAT pin, it could, depending on your power source, carry voltages that would be dangerous to any other pin on the board.

QSPI:
These pins are part of the Motorola Queued Serial Peripheral Interface and are used by any code using the QSPI or PicoBus. If you are not using the QSPI or PicoBUS in your application these pins may be used as general purpose I/O. These lines consist of data line, chip selects and clock lines

TMR:
These pins are natively controlled by the Configurable Time Module in the MC68CK338. There are two possible native functions for each of these pins. Either it is linked to a Single Action timer module which is used to capture a single input or output event, or it is part of a Double action timer module that can deal with two stage events like pulse detection/measurement and Pulse Width Modulation.

UART:
This designation implies that the pin is used in the RS232 communication system. These pins are crucial to how the CF1 talks to the outside world in development and any other situation in which you wish to interact with the Persistor.

IRQ:
The pins bearing the IRQ designation are hardware interrupt pins by default but can be used as general purpose I/O if necessary, it should be noted however that these pins must be either floating or pulled high at startup. Their function as hardware interrupts is selected at system startup and having them low at that time would cause an interrupt condition from which it could be very difficult to recover.

Connector C Pin List

Bus Expansion

The CF1 has been designed to allow for easy bus expansion and addition of memory mapped peripherals. With all of the address and bus lines brought out on tenth inch grids, prototyping is easy and the hardware development cycle for memory mapped peripherals can be almost as fast as your software cycle. Two chips selects have been left open for your bus related projects. These are CS8 and CS10 and are described in detail in the API reference section titled Chip Select Wrappers. The following are diagrams of the the bus pins as they are brought out to the connectors.

Connector A - Address Bus Pin # Signal Desc Dir Funct Type 1 ADDR1 Address Bus Out BUS A 2 ADDR19 Address Bus Out BUS A 3 ADDR3 Address Bus Out BUS A 4 ADDR2 Address Bus Out BUS A 5 ADDR5 Address Bus Out BUS A 6 ADDR4 Address Bus Out BUS A 7 ADDR7 Address Bus Out BUS A 8 ADDR6 Address Bus Out BUS A 9 ADDR9 Address Bus Out BUS A 10 ADDR8 Address Bus Out BUS A 11 ADDR11 Address Bus Out BUS A 12 ADDR10 Address Bus Out BUS A 13 ADDR13 Address Bus Out BUS A 14 ADDR12 Address Bus Out BUS A 15 ADDR15 Address Bus Out BUS A 16 ADDR14 Address Bus Out BUS A 17 ADDR17 Address Bus Out BUS A 18 ADDR16 Address Bus Out BUS A 19 CLKOUT System Clk Out CLK A 20 ADDR18 Address Bus Out BUS A

Connector B - Data Bus Pin # Signal Desc Dir Funct Type 1 DATA1 Data Bus I/O BUS AwP1M 2 DATA0 Data Bus I/O BUS AwP1M 3 DATA3 Data Bus I/O BUS AwP1M 4 DATA2 Data Bus I/O BUS AwP1M 5 DATA5 Data Bus I/O BUS AwP1M 6 DATA4 Data Bus I/O BUS AwP1M*1 7 DATA7 Data Bus I/O BUS AwP1M 8 DATA6 Data Bus I/O BUS AwP1M 9 DATA9 Data Bus I/O BUS AwP1M 10 DATA8 Data Bus I/O BUS AwP1M 11 DATA11 Data Bus I/O BUS AwP1M 12 DATA10 Data Bus I/O BUS AwP1M 13 DATA13 Data Bus I/O BUS AwP1M 14 DATA12 Data Bus I/O BUS AwP1M 15 DATA15 Data Bus I/O BUS AwP1M 16 DATA14 Data Bus I/O BUS AwP1M 17 /CS8 Chip Select Out CLK A 18 /CS10 Chip Select Out BUS A 19 R/W Read/Write Out BUS AP10K 20 CLKIN Clock Input In CLK *2

Pin Notes:

A Output only signals that are always driven.
Aw Type A output with weak P-channel pullup during reset.
Ao Type A output that can operate in open drain mode.
B Three-state output with pre-high impedance pullup for fast rise.
Bo Type B output that can operate in open drain mode.
Pnn Pull-up resistor value on board.

*1. DATA4 is pulled low with 10K during reset.

*2. CLKIN is connected to the 68338 EXTAL input for the 40kHz crystal. It is an extremely high impedance input and care must be taken not to make unintentional connection to this pin, which would likely cause erratic behavior. Contact the factory for information on using CLKIN with an external precision clock source.

*3. /SHDN is an output signal controlled by the power management circuitry. Your peripheral circuitry can monitor this signal, but only with inputs having less than 100nA leakage and less than 100pF capacitance. When low, all of the CF1 circuitry is powered off. Do not attempt to assert or load this line.

*4. /WAKE is input to the power management circuitry and is pull high with 1M to the internal VBAK volage. External circuitry (coordinated with CF1 driver software) may use this line to pull the CF1 out of suspend mode.

*5. These lines must be left floating, or asserted high at reset.

*6. This line must be floating or asserted high at reset for normal operation. It may be pulled low during reset to disable the onboard PLL clock oscillator and insert an external clock. Contact the factory for application notes.

*7. /RXD and /CTS are inputs to the 68338, but are normally driven by the RS232 driver chip. You can disable the RS232 driver under software control to allow the CF1 to run the UART at CMOS levels.

*8. DS comes out of reset as an active driving bus output, but is not used by the CF1 except when connected to a BDM debugger. When your program gets control, you can define this line as a BUS signal (for decoding), an input signal (though you must not drive into it until you redefine it), or an output signal. The convenient location and the fact that it is less useful as a general purpose control line (since it flails at reset) makes this an ideal pin for diagnostics and timing or profiling your functions with a scope using the fast I/O macros.

*9. All of the QSPI (PicoBUS) signals revert to inputs at reset which means they may assume any state, and that could be trouble for attached SPI devices which could interpret reset flailing as commands, which in turn could have the SPI device do something the CF1 would not like. You should add 10K to 100K pullups to the /CS lines of your SPI devices to prevent trouble.

*10. The PASS pin does not connect to any circuitry on the CF1 and may be used to pass a signal from a top mounted expansion board to another bottom mounted board.

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